Load kernel regs from virtual kernel regs at domain switch (found by Kevin Tian)
authordjm@kirby.fc.hp.com <djm@kirby.fc.hp.com>
Tue, 1 Nov 2005 04:07:56 +0000 (22:07 -0600)
committerdjm@kirby.fc.hp.com <djm@kirby.fc.hp.com>
Tue, 1 Nov 2005 04:07:56 +0000 (22:07 -0600)
xen/arch/ia64/xen/process.c
xen/arch/ia64/xen/regionreg.c
xen/arch/ia64/xen/vcpu.c
xen/arch/ia64/xen/xenmisc.c

index c3eb890a8bc35a8fa819d0c54510c0aeb641cb4f..2c9063e800936875ef79efb0e09127accb77902b 100644 (file)
@@ -83,9 +83,8 @@ void schedule_tail(struct vcpu *next)
     if(VMX_DOMAIN(current)){
        vmx_load_all_rr(current);
     }else{
-           if (rr7 = load_region_regs(current)) {
-                   printk("schedule_tail: change to rr7 not yet implemented\n");
-       }
+           load_region_regs(current);
+            vcpu_load_kernel_regs(current);
     }
 }
 
index 2e0bb6425f9b1196e11a73d45e78d2416905bc78..35277513c2209ac9d5228656d76e46a740d094cf 100644 (file)
@@ -341,23 +341,13 @@ virtualize_rid(struct vcpu *v, unsigned long rrval)
 // rr7 (because we have to to assembly and physical mode
 // to change rr7).  If no change to rr7 is required, returns 0.
 //
-unsigned long load_region_regs(struct vcpu *v)
+void load_region_regs(struct vcpu *v)
 {
        unsigned long rr0, rr1,rr2, rr3, rr4, rr5, rr6, rr7;
        // TODO: These probably should be validated
        unsigned long bad = 0;
 
        if (VCPU(v,metaphysical_mode)) {
-               ia64_rr rrv;
-
-#if 0
-               rrv.rrval = 0;
-               rrv.rid = v->domain->arch.metaphysical_rr0;
-               rrv.ps = PAGE_SHIFT;
-               rrv.ve = 1;
-               rr0 = rrv.rrval;
-               set_rr_no_srlz(0x0000000000000000L, rr0);
-#endif
                rr0 = v->domain->arch.metaphysical_rr0;
                ia64_set_rr(0x0000000000000000L, rr0);
                ia64_srlz_d();
@@ -383,5 +373,4 @@ unsigned long load_region_regs(struct vcpu *v)
        if (bad) {
                panic_domain(0,"load_region_regs: can't set! bad=%lx\n",bad);
        }
-       return 0;
 }
index bcb0428fab77d5a50caa1dc07baf78241d4dbd34..ce38e1d2296e7d61b7d5f14cd1fa9ee84b6b0a3c 100644 (file)
@@ -135,6 +135,18 @@ vcpu_set_gr(VCPU *vcpu, unsigned reg, UINT64 value)
  VCPU privileged application register access routines
 **************************************************************************/
 
+void vcpu_load_kernel_regs(VCPU *vcpu)
+{
+       ia64_set_kr(0, VCPU(vcpu, krs[0]));
+       ia64_set_kr(1, VCPU(vcpu, krs[1]));
+       ia64_set_kr(2, VCPU(vcpu, krs[2]));
+       ia64_set_kr(3, VCPU(vcpu, krs[3]));
+       ia64_set_kr(4, VCPU(vcpu, krs[4]));
+       ia64_set_kr(5, VCPU(vcpu, krs[5]));
+       ia64_set_kr(6, VCPU(vcpu, krs[6]));
+       ia64_set_kr(7, VCPU(vcpu, krs[7]));
+}
+
 IA64FAULT vcpu_set_ar(VCPU *vcpu, UINT64 reg, UINT64 val)
 {
        if (reg == 44) return (vcpu_set_itc(vcpu,val));
@@ -1872,4 +1884,3 @@ IA64FAULT vcpu_ptr_i(VCPU *vcpu,UINT64 vadr,UINT64 addr_range)
        // don't forget to recompute itr_regions
        return (IA64_ILLOP_FAULT);
 }
-
index 1d2d74afb4637b66e1dd1f0b64aa8cafd173a920..aa8ca1124c5e475d34135391631ba63c596d02b8 100644 (file)
@@ -320,6 +320,7 @@ if (!i--) { printk("+",id); i = 1000000; }
                VHPT_ENABLED);
        if (!is_idle_task(current->domain)) {
                load_region_regs(current);
+               vcpu_load_kernel_regs(current);
                    if (vcpu_timer_expired(current)) vcpu_pend_timer(current);
        }
            if (vcpu_timer_expired(current)) vcpu_pend_timer(current);